# File timestamp (UTC): 2021-01-15T18:45:28.998
# NIST Circuit Complexity Project
# https://csrc.nist.gov/projects/circuit-complexity

begin circuit FSE_LiuSim16_4x4_4--rs=178

# Boolean Circuit for a linear system defined by a 16x16 bit-matrix
# Matrix represented as 16 columns: UInt16[0x1941, 0x2182, 0x4234, 0x8468, 0x9411, 0x1822, 0x2344, 0x4688, 0x4119, 0x8221, 0x3442, 0x6884, 0x1194, 0x2218, 0x4423, 0x8846]
# Matrix obtained from: https://github.com/rub-hgi/shorter_linear_slps_for_mds_matrices
# Tally: 16 inputs, 16 outputs, 44 gates (44 XOR)
# Depth: 4

Inputs: x1:x16
Outputs: y1:y16
Internal: t1:t28
GateSyntax: GateName Output Inputs

# Regex find gate in new format: XOR\s([ty]\d+)\s([tyx]\d+)\s([tyx]\d+).*$
# Regex replacing to old format: \1 = XOR\(\2,\3\)

begin SLP
XOR t1 x5 x15
XOR t2 x3 x13
XOR t3 x4 x8
XOR t4 x4 x16
XOR t5 x2 x13
XOR t6 x6 x16
XOR t7 x1 x11
XOR t8 x8 x12
XOR y8 t5 t8
XOR t9 x15 t6
XOR t10 x7 x12
XOR t11 x1 x9
XOR t12 x10 t4
XOR y16 x5 t12
XOR t13 x14 t10
XOR t14 x9 x14
XOR y4 t3 t14
XOR t15 x2 x11
XOR y2 t9 t15
XOR y14 t13 t15
XOR t16 x3 t8
XOR t17 t1 t11
XOR y1 x10 t17
XOR t18 t4 t7
XOR y7 x7 t18
XOR t19 x9 x15
XOR y15 t16 t19
XOR t20 x10 t13
XOR y10 t16 t20
XOR t21 x5 t2
XOR y5 t14 t21
XOR t22 x12 t6
XOR y12 x1 t22
XOR t23 x6 x13
XOR t24 x3 t12
XOR y6 t9 t24
XOR t25 x16 t10
XOR y3 t2 t25
XOR t26 x11 t1
XOR y11 t3 t26
XOR t27 x5 t23
XOR y13 t7 t27
XOR t28 x7 t11
XOR y9 t5 t28
end SLP
end circuit