# File timestamp (UTC): 2021-03-21T12:20:35.707 # NIST Circuit Complexity Project # https://csrc.nist.gov/projects/circuit-complexity begin circuit SKOP15-4x4-GF16--XOR=44--XZLBZ20 # SLP Source: https://doi.org/10.13154/tosc.v2020.i2.120-145 --- https://github.com/xiangzejun/Optimizing_Implementations_of_Linear_Layers # The preamble, metadata, SLP syntax and variable names have been adjusted here to the NIST format # Boolean Circuit for a linear system y = A.x defined by a 16x16 bit-matrix A # Matrix A weights (W): totalW=84, adjW=68, minWInRow=5, maxWInRow=6, minWInCol=6, maxWICol=5 # Matrix represented as 16 rows: vecRows=UInt16[0x9821, 0x1342, 0x2684, 0x4c38, 0x8912, 0x3124, 0x6248, 0xc483, 0x2198, 0x4213, 0x8426, 0x384c, 0x1289, 0x2431, 0x4862, 0x83c4] # Matrix represented as 16 columns: vecCols=UInt16[0x3281, 0x4692, 0x8c24, 0x1948, 0x2318, 0x6429, 0xc842, 0x9184, 0x8132, 0x9246, 0x248c, 0x4819, 0x1823, 0x2964, 0x42c8, 0x8491] # The element in the i-th row and j-th col of A is A[i,j] = 1 & (vecRows[i]>>(j-1)) = 1 & (vecCols[j]>>(i-1)) # Tally: 16 inputs, 16 outputs, 44 gates (44 XOR) # Circuit depth: 7 Inputs: x1:x16 Outputs: y1:y16 Internal: t1:t28 GateSyntax: GateName Output Inputs # Regex to obtain gate (\1), output var (\2) and input vars (\3, \4): (XOR)\s([ty]\d+)\s([tyx]\d+)\s([tyx]\d+).*$ begin SLP XOR t1 x13 x12 XOR t2 x12 x16 XOR t3 x16 x5 XOR t4 x8 x11 XOR t5 x1 t4 XOR t6 x4 t4 XOR t7 t4 t1 XOR t8 t1 x10 XOR t9 x5 t8 XOR t10 x9 t7 XOR t11 t7 x2 XOR t12 x2 t2 XOR y16 t3 t5 XOR t13 t5 x6 XOR t14 t12 x7 XOR t15 t2 x11 XOR t16 t8 t14 XOR y7 t14 x15 XOR t17 x11 x15 XOR t18 x15 t11 XOR y13 t11 t13 XOR t19 t13 x14 XOR y2 t18 t9 XOR y10 t16 x3 XOR t20 t9 x14 XOR t21 x14 x3 XOR t22 x3 t15 XOR y11 t21 t6 XOR t23 t17 t6 XOR t24 t6 t10 XOR t25 t15 y16 XOR y3 x6 t22 XOR y8 t22 t10 XOR t26 x10 x7 XOR t27 t10 y16 XOR y6 t19 t23 XOR y15 t26 t23 XOR y12 t23 t25 XOR y9 t27 y13 XOR y4 x7 t24 XOR y1 t25 t20 XOR y5 t24 t20 XOR t28 t20 y9 XOR y14 t28 y10 end SLP end circuit