# File timestamp (UTC): 2021-03-21T12:20:35.708
# NIST Circuit Complexity Project
# https://csrc.nist.gov/projects/circuit-complexity

begin circuit SKOP15-4x4-GF16-inv--XOR=44--XZLBZ20

# SLP Source: https://doi.org/10.13154/tosc.v2020.i2.120-145 --- https://github.com/xiangzejun/Optimizing_Implementations_of_Linear_Layers
# The preamble, metadata, SLP syntax and variable names have been adjusted here to the NIST format

# Boolean Circuit for a linear system y = A.x defined by a 16x16 bit-matrix A
# Matrix A weights (W): totalW=88, adjW=72, minWInRow=5, maxWInRow=7, minWInCol=7, maxWICol=5
# Matrix represented as 16 rows: vecRows=UInt16[0xd941, 0x9182, 0x1234, 0x2468, 0x9d14, 0x1928, 0x2143, 0x4286, 0x41d9, 0x8291, 0x3412, 0x6824, 0x149d, 0x2819, 0x4321, 0x8642]
# Matrix represented as 16 columns: vecCols=UInt16[0x7341, 0x84c2, 0x1894, 0x3128, 0x3714, 0x482c, 0x8149, 0x1382, 0x4173, 0xc284, 0x9418, 0x2831, 0x1437, 0x2c48, 0x4981, 0x8213]
# The element in the i-th row and j-th col of A is A[i,j] = 1 & (vecRows[i]>>(j-1)) = 1 & (vecCols[j]>>(i-1))

# Tally: 16 inputs, 16 outputs, 44 gates (44 XOR)
# Circuit depth: 8

Inputs: x1:x16
Outputs: y1:y16
Internal: t1:t28
GateSyntax: GateName Output Inputs

# Regex to obtain gate (\1), output var (\2) and input vars (\3, \4): (XOR)\s([ty]\d+)\s([tyx]\d+)\s([tyx]\d+).*$
begin SLP
XOR t1 x1 x9
XOR t2 x3 x12
XOR t3 x9 x5
XOR t4 x5 x13
XOR t5 x10 t3
XOR t6 t3 x14
XOR t7 x12 t1
XOR t8 x11 x16
XOR t9 x16 t1
XOR t10 x14 t8
XOR t11 t10 t7
XOR t12 t5 x2
XOR t13 x2 x7
XOR t14 x13 t13
XOR t15 t6 x6
XOR t16 x6 x15
XOR t17 t14 t16
XOR t18 t16 x4
XOR t19 t13 x8
XOR t20 x15 x8
XOR t21 x8 t4
XOR y6 t18 t2
XOR t22 x7 x4
XOR y7 t22 t9
XOR y14 t11 y7
XOR t23 x4 t4
XOR y2 t19 t8
XOR y15 t20 t7
XOR t24 t1 t17
XOR y9 t4 t24
XOR t25 t24 t12
XOR y12 t7 t15
XOR y16 t9 t12
XOR y3 t2 t21
XOR y8 t21 t12
XOR t26 t12 y14
XOR y11 t8 t23
XOR y4 t23 t15
XOR t27 t26 y6
XOR y5 t17 t27
XOR y1 t15 t25
XOR t28 t25 y2
XOR y13 t27 y1
XOR y10 t28 y13
end SLP
end circuit