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Optimized Threshold Implementations: Number of Shares and Area/Latency Trade-off

March 12, 2019


Ventzislav Nikov - NXP Semiconductors


Joint work with: Dušan Božilov, Miroslav Knežević.

Abstract. Threshold implementation (TI) is a popular hardware masking technique, being used in some of the current most efficient side-channel secure designs. Earlier versions of TI are characterized by the number of input shares being dependant on both security order d and algebraic degree of a function t, namely td + 1. Later, the bound was reduced to d + 1, with the cost of increasing the number of output shares and requirements of the input shares. In this work, we utilize the optimized sharing method to investigate the impact of the number of S-box stages on the area and latency of the final design, with the two extreme cases of fully decomposed S-box and a single stage S-box. Finally, we show the trade-off on d+1 and td + 1 TI, for first- and second-order secure, low-latency and low-energy implementations of the PRINCE block cipher.

Optimized Threshold Implementations: Number of Shares and Area/Latency Trade-off. Click to watch the video.

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Presented at

NIST Threshold Cryptography Workshop 2019


Presentation (PDF)

Event Details


    NIST, Gaithersburg campus

Related Topics

Security and Privacy: cryptography

Created March 12, 2019, Updated June 11, 2021