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Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
An FPGA implementation of the AES algorithm.
Version
1.0 (Firmware)
Type
SOFTWARE
Vendor
GDC Technology (USA), LLC
3500 W. Olive Ave., Suite 940
Burbank, CA 91505
USA
Contacts
Arun Kishore
fips@gdc-tech.com
877-743-2872
Fax: 877-643-2872

AES 1286

   First Validated: 2/16/2010
Operating Environment Algorithm Capabilities
Xilinx FPGA AES-CBC Expand
Xilinx FPGA AES-ECB Expand

Created October 05, 2016, Updated March 08, 2021