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Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
100Gbps FPGA core. AES-XTS 256 bit key, 128 bit multiple length text. Assocated GMAC, 256 bit key, 128 bit multiple length AAD, zero length PT.
Version
XTS_GMAC_CG_1.0 (Firmware)
Type
SOFTWARE
Vendor
Altera Denmark Technology Center
Hoerkaer 12A, 3
Herlev 2730
Denmark
Contacts
Soeren Laursen
slaursen@altera.com
+45 88701912
Morten Stribaek
mstribae@altera.com
+45 88701945

AES 2770

   First Validated: 2/14/2014
Operating Environment Algorithm Capabilities
Mentor Questa Slm 10.2c AES-GMAC Expand
Mentor Questa Slm 10.2c AES-XTS Expand

Created October 05, 2016, Updated March 16, 2023