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Cryptographic Algorithm Validation Program CAVP

Implementation Name
The Cavium OCTEON family of Multi-Core MIPS64 processors has 1 to 48 cores per chip. They integrate next-generation networking I/Os with advanced security, storage, and application hardware acceleration, offering unprecedented throughput and programmability for Layer 2 through Layer 7 processing of intelligent networks.
CN7010, CN7020, CN7120, CN7125, CN7130, CN7230, CN7240, CN7340, CN7350, CN7360, CN7760, CN7770, CN7870, CN7880, CN7890; -AAP, -C
Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054
Maen Suleiman

AES 3301

   First Validated: 3/27/2015
Operating Environment Algorithm Capabilities
Octeon III Family Crypto Engine AES-CBC Expand
Octeon III Family Crypto Engine AES-ECB Expand
Octeon III Family Crypto Engine AES-GCM Expand
Octeon III Family Crypto Engine AES-GMAC Expand

Created October 05, 2016, Updated July 03, 2024