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Cavium security algorithms are implemented via hardware acceleration blocks that are party of the Co-Processor 2 in the MIPs Release 2 architecture. Cavium also offers APIs to allow software interaction and updates that utilize these hardware blocks. Cavium can disable security cores to comply with related export laws and regulations.
Version
CN5010-400BG564-SCP-G
Type
HARDWARE
Vendor
Cavium Networks 805 E Middlefield Road Mountain View, CA 94109 USA
Contacts
Ben Studer ben.studer@caviumnetworks.com
408-482-5491
Fax: 650-625-9761
Eric Dudley eric.dudley@caviumnetworks.com
650-623-7039