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Cryptographic Algorithm Validation Program CAVP

Implementation Name
NITROX III chips implement SHA1/SHA2, 3DES/AES256 CBC, ModMul/ModEx/RSA, GCM and CTR modes, and SP800-90A DRBG. Perf: 5 to 30 Gbps encrypt/hash; 35K to 200K RSA 1024b ops/sec; 6K to 35K RSA 2048b ops/sec. NITROX III microcode also implements protocol-specific acceleration for IPSec and SSL.
Nitrox III Series Die, v1.1
Cavium, Inc.
2315 N. First Street
San Jose, CA 95131
Mike Scruggs
(408) 943-7100
Fax: (408) 577-1992
TA (TAR) Ramanujam
(408) 943-7383
Fax: (408) 577-1992

HMAC 1233

   First Validated: 5/25/2012
Operating Environment Algorithm Capabilities
N/A HMAC-SHA-1 Expand
N/A HMAC-SHA2-224 Expand
N/A HMAC-SHA2-256 Expand
N/A HMAC-SHA2-384 Expand
N/A HMAC-SHA2-512 Expand

Created October 05, 2016, Updated July 03, 2024