Cryptographic Algorithm Validation Program CAVP

Description
The Xilinx AES Lite IP core provides a light-weight implementation of AES with a wide range of configuration options for designs that are constrained on logic resources.
Version
v1.0
Type
FIRMWARE
Vendor
Xilinx, Inc.
Salarpuria Sattva Knowledge City
Survey no 83,1
HITEC City, Hyderabad, Telangana 500032
India
Contacts
Dev Maiti
devm@xilinx.com
+91-74068-49484

C1609 First Validated: 3/3/2020

Operating Environment Algorithm Capabilities
QuestaSim 10.7c
  • processor: QuestaSim 10.7c
AES-CFB128
  • Direction: Decrypt, Encrypt
  • Key Length: 128, 192, 256
QuestaSim 10.7c
  • processor: QuestaSim 10.7c
AES-ECB
  • Direction: Decrypt, Encrypt
  • Key Length: 128, 192, 256
QuestaSim 10.7c
  • processor: QuestaSim 10.7c
AES-XTS
  • Direction: Decrypt, Encrypt
  • Key Length: 128
  • Payload Length: 128, 256, 65536
  • Tweak Mode: Hex, Number
QuestaSim 10.7c
  • processor: QuestaSim 10.7c
AES-XTS
  • Direction: Decrypt, Encrypt
  • Key Length: 256
  • Payload Length: 128, 256, 65536
  • Tweak Mode: Hex, Number

Created October 05, 2016, Updated January 22, 2021