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Root-cause Analysis of the Side Channel Leakage from ASCON implementations

June 21, 2023


Zhenyuan Liu - Worcester Polytechnic Institute


Root-Cause Analysis of Side Channel Leakage (SCL) aims to identify the components of observed SCL. We analyze ASCON’s SCL for two variants implemented on a RISC-V SoC: a hardware coprocessor with an iterated implementation of ASCON-128, and a software implementation of ASCON-128 on RISC-V (RV32IMC). We use gate-level power simulation to find the power traces, and to identify which portions of the hardware/software implementation show most leakage of the secret key. Our analysis breaks out the leakage according to the major processing phases of ASCON and according to their implementation. We also compare the simulated traces with measurements collected from a 180nm ASIC implementation of the same design.

Presented at

Lightweight Cryptography Workshop 2023 [Virtual]

Event Details



Related Topics

Security and Privacy: lightweight cryptography

Created June 20, 2023, Updated June 22, 2023