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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Cryptographic Module (Gen2 TRANSEC) FPGA
Description
The Comtech TRANSEC features an FPGA to perform bulk encryption/decryption for Ethernet data traffic via Comtech Satellite Modems, and firmware to provide the cryptographic functions needed to act as an endpoint for secure TLS- and SSH-based M&C traffic.
Version
12-28-2021
Type
HARDWARE
Vendor
Comtech Satellite Network Technologies, Inc.
2114 W 7th Street
Tempe, AZ 85281
United States
Contacts
Christopher Mauro
chris.mauro@comtech.com
480-333-2325

A2341

   First Validated: 2/15/2022
Operating Environment Algorithm Capabilities
Xilinx Artix 7 XC7A50T Expand
    		AES-CBC Expand
    Xilinx Artix 7 XC7A50T Expand
      		AES-CTR Expand

      Created October 05, 2016, Updated March 16, 2023