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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
ZyFLEX AES Core
Description
The ZyFLEX AES Core is a comprehensive hardware IP implementation of AES in synthesizable Verilog code. The core can be synthesized as encryption engine, decryption engine or encryption/decryption engine, and can be targeted at commercial FPGAs or ASIC implementation.
Version
1.0 (Firmware)
Type
SOFTWARE
Vendor
ZyFLEX Technologies, Inc.
4F,No.5-2, Industry E. 9th Rd., Science park Hsinchu
Hsinchu 30075
Taiwan, R.O.C.
Contacts
Nick Tseng
Nick.Tseng2@zyxel.com.tw
+886-3-5679168
Fax: +886-3-5679188

AES 1671

   First Validated: 6/7/2011
Operating Environment Algorithm Capabilities
Modelsim 6.4a Verilog simulator AES-CCM Expand
Modelsim 6.4a Verilog simulator AES-OFB Expand

Created October 05, 2016, Updated March 16, 2023