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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES Algorithm
Description
The AES Algorithm operates in an FPGA in the Counter Mode. The counter input is based on an incrementing counter. The algorithms are stored in memory operating in a FIPS-approved mode. One of the four algorithms is selected for use and loaded. The module accepts up to eight keys which are externally generated and loaded.
Version
091-3192-001 (Firmware)
Type
SOFTWARE
Vendor
Rockwell Collins, Inc.
400 Collins Road, MS 183-100
Cedar Rapids, IA 52411
USA
Contacts
Jack Edington
N/A
(319) 295-5997
Fax: N/A

AES 169

   First Validated: 9/7/2004
Operating Environment Algorithm Capabilities
Windows XP AES-CTR Expand
Windows XP AES-ECB Expand

Created October 05, 2016, Updated March 07, 2024