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Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
AES Core G2 is Algotronix' comprehensive hardware IP core implementation of AES in synthesisable VHDL code. All NIST recommended modes and key lengths are supported. The core can be synthesised as an encryptor, decryptor or encryptor/decryptor and can be targeted at Xilinx, Altera and Actel FPGAs or for ASIC implementation.
Version
SP1 (Firmware)
Type
SOFTWARE
Vendor
Algotronix Ltd.
P.O. Box 23116
Edinburgh, Scotland EH8 8YB
United Kingdom
Contacts
Tom Kean
cores@algotronix.com
+441315569242
Fax: +448700525069

AES 374

   First Validated: 3/16/2006
Operating Environment Algorithm Capabilities
Simulator: Aldec Active HDL version 6.1 AES-CBC Expand
Simulator: Aldec Active HDL version 6.1 AES-CFB1 Expand
Simulator: Aldec Active HDL version 6.1 AES-CFB128 Expand
Simulator: Aldec Active HDL version 6.1 AES-CFB8 Expand
Simulator: Aldec Active HDL version 6.1 AES-CTR Expand
Simulator: Aldec Active HDL version 6.1 AES-ECB Expand
Simulator: Aldec Active HDL version 6.1 AES-OFB Expand

Created October 05, 2016, Updated July 03, 2024