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Cryptographic Algorithm Validation Program CAVP

Description
Hardware implementation of ML-DSA (FIPS 204) digital signatures and SHAKE (FIPS 202) extendable-output functions. Featuring dedicated 8-way parallel NTT and first-order masked Keccak (TI3) cryptographic engines on AMD Zynq UltraScale+ FPGA. Supports all three ML-DSA security levels (ML-DSA-44, ML-DSA-65, ML-DSA-87) with runtime parameter selection.
Version
1.0
Type
HARDWARE
Vendor
Codebat Technologies, Inc.
131 Continental Dr, Suite 305
Newark, Delaware 19713
USA
Contacts
Leo Kao
[email protected]
+1(302)302-9165

A8288

   First Validated: 4/23/2026
Operating Environment Algorithm Capabilities
AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
    ML-DSA KeyGen Expand
    AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
      ML-DSA SigGen Expand
      AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
        ML-DSA SigGen Expand
        AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
          ML-DSA SigVer Expand
          AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
            ML-DSA SigVer Expand
            AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
              SHAKE-128 Expand
              AMD Zynq UltraScale+ MPSoC XCZU5EV Expand
                SHAKE-256 Expand

                Created October 05, 2016, Updated September 22, 2026