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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Palo Alto Networks PA-500, PA-2020, PA-2050, PA-4020, PA-4050, PA-4060
Description
Delivered as a purpose-built platform, Palo Alto Networks next-generation firewalls bring visibility and control over applications, users and content back to the IT department using three identification technologies: App-ID, User-ID and Content-ID.
Version
0.9.8l-24 (Firmware)
Type
SOFTWARE
Vendor
Palo Alto Networks
232 E. Java Dr.
Sunnyvale, CA 94089
USA
Contacts
Nick Campagna
certifications@paloaltonetworks.com
(408) 738-7700

AES 1378

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon AES-CBC Expand
Intel Dual Core Xeon AES-CBC Expand
Cavium Octeon AES-CFB1 Expand
Intel Dual Core Xeon AES-CFB1 Expand
Cavium Octeon AES-CFB128 Expand
Intel Dual Core Xeon AES-CFB128 Expand
Cavium Octeon AES-CFB8 Expand
Intel Dual Core Xeon AES-CFB8 Expand
Cavium Octeon AES-ECB Expand
Intel Dual Core Xeon AES-ECB Expand
Cavium Octeon AES-OFB Expand
Intel Dual Core Xeon AES-OFB Expand

RSA 675

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon RSA KeyGen (FIPS186-2): Expand
Intel Dual Core Xeon RSA KeyGen (FIPS186-2): Expand
Cavium Octeon RSA SigGen (FIPS186-2) Expand
Intel Dual Core Xeon RSA SigGen (FIPS186-2) Expand
Cavium Octeon RSA SigVer (FIPS186-2) Expand
Intel Dual Core Xeon RSA SigVer (FIPS186-2) Expand

SHS 1259

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon SHA-1 Expand
Intel Dual Core Xeon SHA-1 Expand
Cavium Octeon SHA2-224 Expand
Intel Dual Core Xeon SHA2-224 Expand
Cavium Octeon SHA2-256 Expand
Intel Dual Core Xeon SHA2-256 Expand
Cavium Octeon SHA2-384 Expand
Intel Dual Core Xeon SHA2-384 Expand
Cavium Octeon SHA2-512 Expand
Intel Dual Core Xeon SHA2-512 Expand

DSA 451

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon DSA KeyGen (FIPS186-2): Expand
Intel Dual Core Xeon DSA KeyGen (FIPS186-2): Expand
Cavium Octeon DSA PQGGen (FIPS186-2): Expand
Intel Dual Core Xeon DSA PQGGen (FIPS186-2): Expand
Cavium Octeon DSA SigGen (FIPS186-2): Expand
Intel Dual Core Xeon DSA SigGen (FIPS186-2): Expand
Cavium Octeon DSA SigVer (FIPS186-2): Expand
Intel Dual Core Xeon DSA SigVer (FIPS186-2): Expand

RNG 760

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon RNG ANSI X9.31: Expand
Intel Dual Core Xeon RNG ANSI X9.31: Expand

HMAC 810

   First Validated: 8/12/2010
Operating Environment Algorithm Capabilities
Cavium Octeon HMAC-SHA-1 Expand
Intel Dual Core Xeon HMAC-SHA-1 Expand
Cavium Octeon HMAC-SHA2-256 Expand
Intel Dual Core Xeon HMAC-SHA2-256 Expand

TDES 950

   First Validated: 6/3/2010
Operating Environment Algorithm Capabilities
Cavium Octeon TDES-CBC Expand
Intel Dual Core Xeon TDES-CBC Expand
Cavium Octeon TDES-CFB64 Expand
Intel Dual Core Xeon TDES-CFB64 Expand
Cavium Octeon TDES-CFB8 Expand
Intel Dual Core Xeon TDES-CFB8 Expand
Cavium Octeon TDES-ECB Expand
Intel Dual Core Xeon TDES-ECB Expand
Cavium Octeon TDES-OFB Expand
Intel Dual Core Xeon TDES-OFB Expand

Created October 05, 2016, Updated March 16, 2023