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Cryptographic Algorithm Validation Program CAVP

Description
A digital cinema standalone integrated media block that is compliant with DCI specifications and SMPTE digital cinema standards. The supported features include JPEG2000 decoding, AES decryption, key management, and logging.
Version
2.0.11 (Firmware)
Type
UNKNOWN
Vendor
GDC Technology (USA) LLC
1016 West Magnolia Boulevard
Burbank, California 91506
USA
Contacts
Pranay Kumar
pranay@gdc-tech.com
(852) 2507 9565
Fax: (852) 2579 1131
ChernYue Kwok
Chernyue.kwok@gdc-tech.com
(852) 2507 9552
Fax: (852) 2579 1131

DRBG 1914

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ Counter DRBG Expand

Component 1650

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ KDF TLS Expand

SHS 4149

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ SHA-1 Expand
Xilinx Zynq Ultrascale+ SHA2-256 Expand

RSA 2762

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ RSA KeyGen (FIPS186-4) Expand
Xilinx Zynq Ultrascale+ RSA SigGen (FIPS186-4) Expand
Xilinx Zynq Ultrascale+ RSA SigVer (FIPS186-4) Expand

HMAC 3403

   First Validated: 1/26/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ HMAC-SHA-1 Expand

Component 1651

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ RSA Decryption Primitive Expand

AES 5122

   First Validated: 1/19/2018
Operating Environment Algorithm Capabilities
Xilinx Zynq Ultrascale+ AES-CBC Expand

Created October 05, 2016, Updated March 16, 2023