Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
The SRX4600 is a high-performance, next-generation firewall supporting cloud-enabled enterprise data center, campus or service provider networks. It offers high-scale security services while providing scalability, ease of management, secure connectivity, and advanced threat mitigation capabilities.
Version
Junos OS 18.1R1 (Firmware)
Type
SOFTWARE
Vendor
Juniper Networks, Inc.
1133 Innovation Way
Sunnyvale, CA 94089
USA
Contacts
Bill Shelton
bshelton@juniper.net
408-745-2000
Fax: 408-745-2001
Vann (Vanna) Nguyen
vann@juniper.net
408-745-2000
Fax: 408-745-2001

ECDSA 1455 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 ECDSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5 ECDSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5 ECDSA SigVer (FIPS186-4) Expand

RSA 2928 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 RSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5 RSA SigGen (FIPS186-2) Expand
Intel(R) Xeon(R) CPU E5 RSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5 RSA SigVer (FIPS186-4) Expand

SHS 4374 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 SHA-1 Expand
Intel(R) Xeon(R) CPU E5 SHA2-224 Expand
Intel(R) Xeon(R) CPU E5 SHA2-256 Expand
Intel(R) Xeon(R) CPU E5 SHA2-384 Expand
Intel(R) Xeon(R) CPU E5 SHA2-512 Expand

AES 5454 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 AES-CBC Expand
Intel(R) Xeon(R) CPU E5 AES-CTR Expand
Intel(R) Xeon(R) CPU E5 AES-ECB Expand

DRBG 2138 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 HMAC DRBG Expand

TDES 2742 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 TDES-CBC Expand

HMAC 3612 Expand All First Validated: 5/25/2018

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5 HMAC-SHA-1 Expand
Intel(R) Xeon(R) CPU E5 HMAC-SHA2-224 Expand
Intel(R) Xeon(R) CPU E5 HMAC-SHA2-256 Expand
Intel(R) Xeon(R) CPU E5 HMAC-SHA2-512 Expand

Created October 05, 2016, Updated December 01, 2020