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Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
Optimized hardware cryptographic module used in custom silicon implementations which need to support security applications.
Version
1.0 (Firmware)
Type
SOFTWARE
Vendor
LSI Corporation
1501 McCarthy Boulevard
Milpitas, CA 95035
USA
Contacts
Lav Ivanovic
Lav.D.Ivanovic@lsi.com
408- 433-7248
Fax: 408- 954-4430

AES 617

   First Validated: 8/7/2007
Operating Environment Algorithm Capabilities
Cadence verilog hardware simulator AES-CBC Expand
Cadence verilog hardware simulator AES-CFB1 Expand
Cadence verilog hardware simulator AES-CFB128 Expand
Cadence verilog hardware simulator AES-CFB8 Expand
Cadence verilog hardware simulator AES-CTR Expand
Cadence verilog hardware simulator AES-ECB Expand
Cadence verilog hardware simulator AES-OFB Expand

Created October 05, 2016, Updated July 03, 2024