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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Beyond AES-XTS
Description
The AES-XTS IP Core is part of a suite of algorithms for FPGA or ASIC implementation provided by Beyond Semiconductor.
Version
BYSI-AES-XTS
Type
HARDWARE
Vendor
Beyond Semiconductor
Brnciceva 41g
1231 Ljubljana-Crnuce, x x
Slovenia, EU
Contacts
Matjaz Breskvar
cavp@beyondsemi.com

C1453

   First Validated: 12/23/2019
Operating Environment Algorithm Capabilities
Beyond AES-XTS Expand
    		AES-ECB Expand
    Beyond AES-XTS Expand
      		AES-XTS Expand
      Beyond AES-XTS Expand
        		AES-XTS Expand

        Created October 05, 2016, Updated March 07, 2024