Cryptographic Algorithm Validation Program CAVP

Implementation Name

Description

The Marvell Bravera SC5 SSD controllers enable next-generation solid-state drives for cloud and data center flash storage applications. The products in the Bravera SSD family - MV-SS1331 and MV-SS1333 support 16 high performance NAND channels respectively. The Bravera SC5 SSD controllers are NVMe 1.4b compliant and feature end-to-end data protection with support for up to 4 PCIe lanes, or a dual port up to 2 PCIe lanes per port. The flash controller issues read, write, or erase commands to the NAND and has a hardware RAID engine. Its error correction engine, the Marvell 5th generation of NANDEdge, uses low-density parity coding (LDPC) that is compatible with a variety of NAND types: SLC, MLC, TLC, and QLC from all NAND Vendors. The Bravera SC5 SSD controllers features 72-bit DDR interface with the option of using either DDR4 or LPDDR4X and has 10 embedded processor cores: Arm Cortex-R8 cores plus additional Cortex-M7 cores for providing further flexibility. In addition, a Cortex-M3 processor core with integrated instruction/data SRAM and crypto engines (AES, SHA, RSA, ECC) in a secure boundary handles the security (TCG) standards for all secure drive control and key management. Featuring ultra low latency (< 6us) can enable SSD storage solutions that offer levers to control and meter performance at the drive level being able to offload hypervisors and fee up host system resources.

Version

IROM version 1.A5.08.0-32

Type

FIRMWARE

Vendor

Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054
USA

Contacts

Minda Zhang
978-760-4755