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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Media_AES/XTS_HW_Engine
Description
A high-speed, low gate count AES hardware module supporting various modes of operation, including AES-XTS.
Version
mdaes_insignia_08012012 (Firmware)
Type
SOFTWARE
Vendor
Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054
USA
Contacts
Wayne Datwyler
(408) 222-2500
Robert Carden
(408) 222-2500

AES 4530

   First Validated: 6/9/2017
Operating Environment Algorithm Capabilities
Synopsys VCS simulation environment, version H-2013.06-SP1-7 AES-CBC Expand
Synopsys VCS simulation environment, version H-2013.06-SP1-7 AES-CTR Expand
Synopsys VCS simulation environment, version H-2013.06-SP1-7 AES-ECB Expand
Synopsys VCS simulation environment, version H-2013.06-SP1-7 AES-XTS Expand
Synopsys VCS simulation environment, version H-2013.06-SP1-7 AES-XTS Expand

Created October 05, 2016, Updated September 22, 2026