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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Curtiss-Wright Pipelined AES-XTS FPGA Core
Description
VHDL implementation of a pipelined AES-XTS core. Simulated in Vivado 2021.2.
Version
1.0
Type
HARDWARE
Vendor
Curtiss-Wright
2600 Paramount Place, Suite 200
Fairborn, Ohio 45324
USA
Contacts
Jeff Biviano
[email protected]
9376105446

A5793

   First Validated: 9/19/2024
Operating Environment Algorithm Capabilities
Xilinx Ultrascale FPGA Simulator Vivado 2021.2 Expand
    		AES-XTS Testing Revision 2.0 Expand

    Created October 05, 2016, Updated September 22, 2026