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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
QSE-IP-86b
Description
The Rambus Quantum Safe Engine (QSE) IP provides Quantum Safe Cryptography acceleration for ASIC, SoC and FPGA devices. The QSE supports the FIPS 203 ML-KEM and FIPS 204 ML-DSA standards. The embedded QSE core firmware allows the core functionality to be updated to adapt to potential future updates in the NIST specifications.
Version
1.2
Type
HARDWARE
Vendor
Rambus Inc.
4453 North First Street, Suite 100
San Jose, California 95134
United States
Contacts
Stuart Kincaid
skincaid@rambus.com

A6658

   First Validated: 3/7/2025
Operating Environment Algorithm Capabilities
QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
    		ML-DSA KeyGen Expand
    QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
      		ML-DSA SigGen Expand
      QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
        		ML-DSA SigVer Expand
        QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
          		ML-KEM EncapDecap Expand
          QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
            		ML-KEM KeyGen Expand
            QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
              		SHA3-256 Expand
              QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
                		SHA3-512 Expand
                QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
                  		SHAKE-128 Expand
                  QSE Firmware 2025-01-22-49fd6ac6 on AMD ZCU102 AMD Zynq UltraScale+ MPSoC ZCU102 Expand
                    		SHAKE-256 Expand

                    Created October 05, 2016, Updated April 03, 2025