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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
MachXO5-NX Root-of-Trust
Description
This implementation consists of dedicated hardware cryptographic modules embedded within the Lattice MachXO5-55TD FPGA. The hardware crypto engine performs the core algorithmic computations, ensuring deterministic execution and performance acceleration. The programmable fabric handles the ingress and egress of user data and implements higher-level protocol logic and additional algorithmic components as required.
Version
X05-55TD
Type
HARDWARE
Vendor
Lattice Semiconductor Corporation
5555 NE Moore Ct
Hillsboro, Oregon 97124
United States
Contacts
Mehryar Rahmatian
[email protected]
+1-503-268-8000
Fax: +1-503-268-8347

A8115

   First Validated: 3/16/2026
Operating Environment Algorithm Capabilities
MachXO5-NX RoT Expand
    		AES-CBC Expand
    MachXO5-NX RoT Expand
      		AES-ECB Expand
      MachXO5-NX RoT Expand
        		AES-GCM Expand
        MachXO5-NX RoT Expand
          		ECDSA SigGen (FIPS186-5) Expand
          MachXO5-NX RoT Expand
            		ECDSA SigVer (FIPS186-5) Expand
            MachXO5-NX RoT Expand
              		SHA2-384 Expand
              MachXO5-NX RoT Expand
                		SHA2-512 Expand

                Created October 05, 2016, Updated September 22, 2026