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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
SYMM1 Hardware Block
Description
XCVU095 FPGA AES block implemented in RTL within the programmable logic that provides FIPS140-3 compliant AES encryption and decryption operations for several AES modes
Version
0xA500
Type
HARDWARE
Vendor
Ranix Inc.
RANIX Bldg. 25, Eonju-ro 135-gil
Gangnam-gu, seoul, Region 06053
Korea
[email protected]
+82-2-584-5516 ext 224
Contacts
Je-Seok Yoon
[email protected]
+82-2-584-5516 (ext 224)
Fax: +82-2-584-5528

A8777

   First Validated: 7/16/2026
Operating Environment Algorithm Capabilities
SYMM1 Hardware Block Expand
    		AES-CBC Expand
    SYMM1 Hardware Block Expand
      		AES-CCM Expand
      SYMM1 Hardware Block Expand
        		AES-CFB128 Expand
        SYMM1 Hardware Block Expand
          		AES-CMAC Expand
          SYMM1 Hardware Block Expand
            		AES-CTR Expand
            SYMM1 Hardware Block Expand
              		AES-ECB Expand
              SYMM1 Hardware Block Expand
                		AES-GCM Expand
                SYMM1 Hardware Block Expand
                  		AES-GMAC Expand
                  SYMM1 Hardware Block Expand
                    		AES-OFB Expand

                    Created October 05, 2016, Updated September 22, 2026