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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Rock-solid 100Gb/s AES-GCM/XTS interleaving Crypto IP
Description
An AES cryptographic hardware IP core supporting 128-bit and 256-bit key lengths in AES-CTR, AES-ECB, AES-GCM, AES-GMAC, AES-XTS, and AES-XPN modes. The core supports encryption, decryption, and multi-channel interleaving. The IP core is implemented in synthesizable Verilog RTL for FPGA and ASIC designs.
Version
1.0
Type
FIRMWARE
Vendor
Rock-solid Microelectronics (Suzhou Shanyuan Microelectronics Co., Ltd.)
A1-303, No. 333 Songbei Road
Suzhou, Jiangsu 215299
China
Contacts
Shuai Chen
[email protected]
17715681226

A8851

   First Validated: 8/12/2026
Operating Environment Algorithm Capabilities
Synopsys VCS AES-CTR Expand
Synopsys VCS AES-ECB Expand
Synopsys VCS AES-GCM Expand
Synopsys VCS AES-GMAC Expand
Synopsys VCS AES-XPN Expand
Synopsys VCS AES-XTS Testing Revision 2.0 Expand

Created October 05, 2016, Updated September 22, 2026