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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
QeM QRNG - CTR_DRBG
Description
CTR_DRBG (SP 800-90A) using AES-256 (FIPS 197), configured without a derivation function; seedlen = 384 bits, 256-bit security strength, with reseed support. It is reseeded from the CMAC-conditioned entropy source and generates the module random output. Tested under ACVP as ctrDRBG. The algorithm is implemented for the Xilinx Artix UltraScale+ XCAU25P-2FFVB676I FPGA.
Version
v2.0.0
Type
FIRMWARE
Vendor
Quantum eMotion Corp
2300 Boul. Alfred-Nobel
Montreal, Quebec H4S 2A4
Canada
Contacts
Wayne Teeple
[email protected]
6135138443

A8859

   First Validated: 8/13/2026
Operating Environment Algorithm Capabilities
Xilinx Vivado xsim 2025.2 Expand
    		Counter DRBG Expand

    Created October 05, 2016, Updated September 22, 2026