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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES G3
Description
AES G3 is Algotronix' next generation comprehensive hardware IP core implementation of AES in synthesisable VHDL code. All NIST recommended modes and key lengths are supported. The core can be synthesised as an encryptor, decryptor or encryptor/decryptor and can be targeted at Xilinx, Altera and Actel FPGAs or for ASIC implementation.
Version
2.0 (Firmware)
Type
SOFTWARE
Vendor
Algotronix Ltd.
P.O. Box 23116
Edinburgh, Scotland EH8 8YB
United Kingdom
Contacts
Tom Kean
tom@algotronix.com
+44-131-556-9242
Fax: +44-870-052-5069

AES 953

   First Validated: 12/12/2008
Operating Environment Algorithm Capabilities
Aldex Active HDL 6.1 AES-CBC Expand
Aldex Active HDL 6.1 AES-CFB1 Expand
Aldex Active HDL 6.1 AES-CFB128 Expand
Aldex Active HDL 6.1 AES-CFB8 Expand
Aldex Active HDL 6.1 AES-CTR Expand
Aldex Active HDL 6.1 AES-ECB Expand
Aldex Active HDL 6.1 AES-OFB Expand

Created October 05, 2016, Updated August 08, 2024