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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
DMPR 30233242
Description
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included in multiple QorIQ Integrated Communications Processors and co-processors, including: C291, C292, C293, T4240r2, and T4160r2.
Version
CAVP_DMPR_30233242_C290R1 (Firmware)
Type
SOFTWARE
Vendor
NXP Semiconductor
6501 William Cannon West
Austin, TX 78735
USA
Contacts
Geoffrey Waters
[email protected]
512-895-2069
Tom Tkacik
[email protected]
480-814-3299

DSA 773

   First Validated: 6/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 DSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 DSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 DSA SigVer (FIPS186-4) Expand

ECDSA 422

   First Validated: 6/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA SigVer (FIPS186-4) Expand

Component 201

   First Validated: 12/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 RSA Signature Primitive Expand

RSA 1434

   First Validated: 12/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 RSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 RSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 RSA SigVer (FIPS186-4) Expand

Created October 05, 2016, Updated April 03, 2025