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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
DMPR 30231242
Description
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs plus Descriptor Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's DHSA 30231242 is included in the QorIQ Integrated Communications Processor: T1040.
Version
CAVP_DMPR_30231242_T1040R1 (Firmware)
Type
SOFTWARE
Vendor
NXP Semiconductor
6501 William Cannon West
Austin, TX 78735
USA
Contacts
Geoffrey Waters
[email protected]
512-895-2069
Tom Tkacik
[email protected]
480-814-3299

DSA 774

   First Validated: 6/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 DSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 DSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 DSA SigVer (FIPS186-4) Expand

Component 199

   First Validated: 12/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 RSA Signature Primitive Expand

ECDSA 423

   First Validated: 6/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 ECDSA SigVer (FIPS186-4) Expand

RSA 1432

   First Validated: 12/20/2013
Operating Environment Algorithm Capabilities
Chronologic VCS simulator, vcs D-2010.06-04 RSA KeyGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 RSA SigGen (FIPS186-4) Expand
Chronologic VCS simulator, vcs D-2010.06-04 RSA SigVer (FIPS186-4) Expand

Created October 05, 2016, Updated April 03, 2025