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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES High Performance Core (AES_HP)
Description
The AES High Performance Core is a hardware implementation of the Rijndael Block Cipher Algorithm. It supports all NIST recommended modes of operation - ECB, CBC, OFB, CFB-1, CFB-8, CFB-128 and CTR mode. Counter with CBC-MAC mode (CCM) is also supported. 200 MHz operation at 0.13um. 2100 Mbit/s throughput.
Version
T-CS-EN-0010-100; Version Rel 1.0
Type
HARDWARE
Vendor
Cadence Design Systems, Inc.
1 The Alba Campus
Livingston, West Lothian EH54 7HH
Scotland, UK
Contacts
Mark Lewis
[email protected]
+44 1506 595083
Fax: +44 1506 595959

AES 115

   First Validated: 12/18/2003
Operating Environment Algorithm Capabilities
N/A AES-CBC Expand
N/A AES-CFB1 Expand
N/A AES-CFB128 Expand
N/A AES-CFB8 Expand
N/A AES-CTR Expand
N/A AES-ECB Expand
N/A AES-OFB Expand

Created October 05, 2016, Updated September 22, 2026