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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES
Description
Altera's high-density high-performance Stratix II and Stratix II GX FPGAscontain built-in AES engine and non-volatile key storage to protectdesigners' intellectual property. Please refer to http://www.altera.com/products/devices/stratix2/features/security/st2-security.html to learn more.
Version
Stratix II
Type
HARDWARE
Vendor
Altera Corp.
101 Innovation Drive
San Jose, CA 95134
USA
Contacts
Christian Plante
cplante@altera.com
408-544-8609
Fax: 408-544-7820
Keone Streicher
kstreich@altera.com
408-544-6827
Fax: 408-544-6402

AES 279

   First Validated: 6/29/2005
Operating Environment Algorithm Capabilities
N/A AES-CTR Expand
N/A AES-ECB Expand

Created October 05, 2016, Updated March 16, 2023