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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
M-AES128X016ADV
Description
M-AES128X016ADV is Macnica's comprehensive hardware IP core implementation of AES in synthesizable Verilog-HDL code. It contains Key-Exp. CCM/CTR/CBC/ECB modes are supported. The core can be synthesized as an encryptor, decryptor or encryptor/decryptor and can be targeted at Altera, Lattice, & Xilinx FPGAs or for ASIC implementation.
Version
1.0 (Firmware)
Type
SOFTWARE
Vendor
MACNICA, Inc.
1-6-3 Shin-Yokohama
Kouhoku-ku
Yokohama, Kanagawa 222-8561
Japan
Contacts
Hajime Nakamura
[email protected]
+81-45-470-9838
Fax: +81-45-470-9857

AES 634

   First Validated: 9/12/2007
Operating Environment Algorithm Capabilities
ncverilog v03.40.(s021) AES-CBC Expand
ncverilog v03.40.(s021) AES-CCM Expand
ncverilog v03.40.(s021) AES-CTR Expand
ncverilog v03.40.(s021) AES-ECB Expand

Created October 05, 2016, Updated September 22, 2026