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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
DMPR 40301443
Description
NXP's DMPR 40301443 is included in multiple QorIQ and Layerscape processors including: LS1023A, LS1026A, LS1043A, LS1046A, LS1048A, and LS1088A. It implements public key algorithms, including DSA, ECDSA, RSA, and key derivation functions.
Version
CAVP_DMPR_40301443 (Firmware)
Type
SOFTWARE
Vendor
NXP Semiconductors
6501 William Cannon Drive West
Austin, TX 78735
USA
Contacts
Geoffrey Waters
[email protected]
512-895-2069
Tom Tkacik
[email protected]
480-814-3299

ECDSA 1068

   First Validated: 3/6/2017
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator ECDSA KeyGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator ECDSA SigGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator ECDSA SigVer (FIPS186-4) Expand

RSA 2402

   First Validated: 3/6/2017
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator RSA KeyGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator RSA SigGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator RSA SigVer (FIPS186-2) Expand
Cadence IES 15.10.009 Verilog simulator RSA SigVer (FIPS186-4) Expand

Component 1127

   First Validated: 3/6/2017
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator KAS-ECC CDH-Component Expand

Component 1126

   First Validated: 3/6/2017
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator KDF IKEv2 Expand
Cadence IES 15.10.009 Verilog simulator KDF TLS Expand

DSA 1183

   First Validated: 3/6/2017
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator DSA KeyGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator DSA SigGen (FIPS186-4) Expand
Cadence IES 15.10.009 Verilog simulator DSA SigVer (FIPS186-4) Expand

Created October 05, 2016, Updated September 22, 2026