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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES-256-CBC
Description
"Altera's various 28-nm FPGA families contain a built-in 256-bit AES engine with both non-volatile and volatile key storage options to protect designers' intellectual property. Please refer to http://www.altera.com/products/devices/stratix-fpgas/about/security/stx-design-security.html?GSA_pos=7&WT.oss_r=1&WT.oss=design%20security to learn more."
Version
AES-SV-RTL-Version-1.20
Type
HARDWARE
Vendor
Altera Corp.
101 Innovation Drive
San Jose, CA 95134
USA
Contacts
Dirk Reese
dreese@altera.com
408-544-7363
Fax: 408-544-6402

AES 1464

   First Validated: 9/21/2010
Operating Environment Algorithm Capabilities
N/A AES-CBC Expand

Created October 05, 2016, Updated March 07, 2024