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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
oTHE AES Verilog Core
Description
This AES Verilog core implements full FIPS PUB 197 (AES), including Cipher, InvCipher, EqInvCipher and KeyExpension in 128, 192 and 256 bits key length. There are several design options for optimizing the design in area or speed. The application Verilog designer can choice the different design options to fit their own designs.
Version
1.0 (Firmware)
Type
SOFTWARE
Vendor
oTHE Technology Inc.
No.749, Wenshan Rd.
Qionglin Township
Hsinchu County, Taiwan 30741
R.O.C.
Contacts
Guide Wang
[email protected]
+886-3-5927463

AES 1576

   First Validated: 2/24/2011
Operating Environment Algorithm Capabilities
Modelsim 5.5f Verilog simulator AES-ECB Expand

Created October 05, 2016, Updated September 22, 2026