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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Macspire IP-0502
Description
Verilog-HDL IP for FPGA. (ALTERA or LATTICE)
Version
A (Firmware)
Type
SOFTWARE
Vendor
MACNICA, Inc.
1-6-3 Shin-Yokohama
Kouhoku-ku
Yokohama, Kanagawa 222-8561
Japan
Contacts
Tamotsu Kato
[email protected]
+81-45-470-9838
Fax: +81-45-470-9857

AES 1848

   First Validated: 10/31/2011
Operating Environment Algorithm Capabilities
Cadence Design Systems, Inc. Incisive Enterprise Simulator - L 10.20.028 AES-CBC Expand
Cadence Design Systems, Inc. Incisive Enterprise Simulator - L 10.20.028 AES-CCM Expand
Cadence Design Systems, Inc. Incisive Enterprise Simulator - L 10.20.028 AES-CTR Expand
Cadence Design Systems, Inc. Incisive Enterprise Simulator - L 10.20.028 AES-ECB Expand

Created October 05, 2016, Updated September 22, 2026