Cryptographic Algorithm Validation Program CAVP

Description
The 50G AES-GCM Crypto IP is a full-featured implementation of the AES-GCM algorithms for IEEE 802.1AE Media Access Control Security (MACsec) specification, targeted for the Xilinx UltraScale and UltraScale+ FPGAs.
Version
50Gb/s Ch AES-GCM (MACsec) v1.0 (Firmware)
Type
FIRMWARE
Vendor
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Contacts
Ravi Sunkavalli
rsunkav@xilinx.com
(408) 879-3557

AES 3954 Expand All First Validated: 4/29/2016

Operating Environment Algorithm Capabilities
Cadence IUS 14.10.018 Verilog Simulator AES-ECB Expand
Cadence IUS 14.10.018 Verilog Simulator AES-GCM Expand
Cadence IUS 14.10.018 Verilog Simulator AES-GMAC Expand

Created October 05, 2016, Updated December 18, 2020