Cryptographic Algorithm Validation Program CAVP

Implementation Name

Description

Altera provides many optimized FPGAs containing a built-in 256-bit AES engine to protect designers' intellectual property from cloning or reverse engineering. For the highest-density & performance FPGAs, get more information about the Stratix III, Stratix IV GX, and Stratix IV E FPGA families at http://www.altera.com/products/devices/stratix-fpgas/about/security/stx-design-security.html. For cost-optimized FPGAs with 3.75-Gbps transceivers, read more about the Arria II GX FPGAs at http://www.altera.com/products/devices/arria-fpgas/arria-ii-gx/overview/architecture/aiigx-architecture.html. For the lowest power FPGAs with a full security suite, review information on the Cyclone III LS FPGAs at http://www.altera.com/products/devices/cyclone3/overview/security/cy3-security.html

Version

Version FIPS197_V1_0

Type

HARDWARE

Vendor

Altera Corp.
101 Innovation Drive
San Jose, CA 95134
USA

Contacts

Paul Ekas
PEKAS@altera.com
408-544-8388
Fax: 408-544-6424
Dirk Reese
DREESE@altera.com
408-544-7363
Fax: 408-544-6402