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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
TRANSEC FPGA
Description
AES 256 counter mode
Version
20191016
Type
HARDWARE
Vendor
Comtech EF Data Corp
2114 W 7th St
Tempe, AZ 85281
USA
Contacts
Peter Russell
prussell@comtechefdata.com
240 243 1854
Fax: 480 333 2540

C1326

   First Validated: 11/6/2019
Operating Environment Algorithm Capabilities
Xilinx Artix 7 XC7A50T Expand
    		AES-CTR Expand
    Xilinx Artix 7 XC7A50T Expand
      		AES-ECB Expand

      Created October 05, 2016, Updated March 07, 2024