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Cryptographic Algorithm Validation Program CAVP

Implementation Name
Description
The design consists of 10 XTS sub-engines. Each XTS sub-engine further consists of an AES engine alone with Cipher Text Stealing circuitry. Each XTS sub-engine has access to a key RAM in order to access the XTS and AES keys. The decryption key is determined ahead of time to allow for symmetric processing.
Version
14369:15c367cd7d19
Type
FIRMWARE
Vendor
Western Digital Corporation
5601 Great Oaks Parkway
San Jose, CA 95119
USA
Contacts
Michael Williamson
Michael.williamson@wdc.com
408-717-8458
Fax: 408-717-7048
David Meyer
david.meyer@wdc.com
303-827-0195
Fax: 408-717-7048

C1973

   First Validated: 7/2/2020
Operating Environment Algorithm Capabilities
Simulator: Cadence NC Version 15.10.022 Expand
    AES-ECB Expand
    Simulator: Cadence NC Version 15.10.022 Expand
      AES-XTS Expand
      Simulator: Cadence NC Version 15.10.022 Expand
        AES-XTS Expand

        Created October 05, 2016, Updated March 16, 2023