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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Secure Boot Block (SBB)
Description
The Secure Boot Block (SBB) provides features for secure system boot, run-time encryption and decryption of Secure Data Objects (SDOs), and authentication functions to enable JTAG port access and eFuse write accesses.
Version
SBBv4
Type
HARDWARE
Vendor
Intel Corporation
2200 Mission College Blvd.
Santa Clara, CA 95054
USA
[email protected]
(408)765-8080
Contacts
Ethernet FIPs Office
[email protected]
503-712-6498

A1553

   First Validated: 6/16/2021
Operating Environment Algorithm Capabilities
Synopsys VCS® (Verilog Compiler Simulator) Expand
    		AES-CBC Expand
    Synopsys VCS® (Verilog Compiler Simulator) Expand
      		AES-CMAC Expand
      Synopsys VCS® (Verilog Compiler Simulator) Expand
        		AES-CTR Expand
        Synopsys VCS® (Verilog Compiler Simulator) Expand
          		AES-ECB Expand
          Synopsys VCS® (Verilog Compiler Simulator) Expand
            		AES-KW Expand
            Synopsys VCS® (Verilog Compiler Simulator) Expand
              		Counter DRBG Expand
              Synopsys VCS® (Verilog Compiler Simulator) Expand
                		ECDSA SigGen (FIPS186-4) Expand
                Synopsys VCS® (Verilog Compiler Simulator) Expand
                  		ECDSA SigVer (FIPS186-4) Expand
                  Synopsys VCS® (Verilog Compiler Simulator) Expand
                    		HMAC-SHA2-256 Expand
                    Synopsys VCS® (Verilog Compiler Simulator) Expand
                      		HMAC-SHA2-384 Expand
                      Synopsys VCS® (Verilog Compiler Simulator) Expand
                        		HMAC-SHA2-512 Expand
                        Synopsys VCS® (Verilog Compiler Simulator) Expand
                          		HMAC-SHA2-512/256 Expand
                          Synopsys VCS® (Verilog Compiler Simulator) Expand
                            		KDF SP800-108 Expand
                            Synopsys VCS® (Verilog Compiler Simulator) Expand
                              		RSA SigVer (FIPS186-4) Expand
                              Synopsys VCS® (Verilog Compiler Simulator) Expand
                                		SHA2-256 Expand
                                Synopsys VCS® (Verilog Compiler Simulator) Expand
                                  		SHA2-384 Expand
                                  Synopsys VCS® (Verilog Compiler Simulator) Expand
                                    		SHA2-512 Expand
                                    Synopsys VCS® (Verilog Compiler Simulator) Expand
                                      		SHA2-512/256 Expand

                                      Created October 05, 2016, Updated September 22, 2026