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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AES-CMAC HW
Description
This is an AES-CMAC used exclusively as conditioning component (vetted) inside an STM32 TRNG HW peripheral. Version number is the concatenation of AES-ECB core and AES-CMAC chaining mode.
Version
184_98
Type
FIRMWARE
Vendor
STMicroelectronics
12 rue Jules Horowitz
Grenoble, Isere 38000
France
Contacts
Pelissier Gilles
[email protected]
+33476584483
Mureddu Ugo
[email protected]
+33 4 42 68 87 96

A5412

   First Validated: 6/21/2024
Operating Environment Algorithm Capabilities
Verilog Simulator Expand
    		AES-CMAC Expand
    Verilog Simulator Expand
      		AES-ECB Expand

      Created October 05, 2016, Updated August 12, 2026