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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
AESA 4.6
Description
NXP's AESA 4.6 is included in multiple i.MX, QorIQ and Layerscape processors including: LS1021A. It implements all key sizes, and modes (ECB, CBC, OFB, CFB, CTR, CCM, CMAC, GCM, GMAC and XTS).
Version
CAVP_AESA_4.6_LS1021A (Firmware)
Type
SOFTWARE
Vendor
NXP Semiconductors
6501 William Cannon Drive West
Austin, TX 78735
USA
Contacts
Geoffery Waters
[email protected]
512-895-2069
Tom Tkacik
[email protected]
480-814-3299

AES 3868

   First Validated: 2/12/2016
Operating Environment Algorithm Capabilities
Cadence IES 15.10.009 Verilog simulator AES-CBC Expand
Cadence IES 15.10.009 Verilog simulator AES-CCM Expand
Cadence IES 15.10.009 Verilog simulator AES-CFB128 Expand
Cadence IES 15.10.009 Verilog simulator AES-CMAC Expand
Cadence IES 15.10.009 Verilog simulator AES-CTR Expand
Cadence IES 15.10.009 Verilog simulator AES-ECB Expand
Cadence IES 15.10.009 Verilog simulator AES-GCM Expand
Cadence IES 15.10.009 Verilog simulator AES-GMAC Expand
Cadence IES 15.10.009 Verilog simulator AES-OFB Expand
Cadence IES 15.10.009 Verilog simulator AES-XTS Expand
Cadence IES 15.10.009 Verilog simulator AES-XTS Expand

Created October 05, 2016, Updated April 03, 2025