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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Qinvicta TwinStar
Description
The Qinvicta TwinStar IP is a Post-Quantum Cryptography accelerator designed for ASIC, SoC, and FPGA platforms. It fully supports the FIPS 203 (ML-KEM) and FIPS 204 (ML-DSA) standards, integrating includes AES, SHA-3, SHAKE, a high-entropy True Random Number Generator (TRNG) and a compliant Deterministic Random Bit Generator (DRBG).
Version
4d4614fb
Type
HARDWARE
Vendor
Qinvicta
8F-2, No. 68, Section 4, Roosevelt Rd.
Zhongzheng Dist., Taipei City 100046
Taiwan (R.O.C.)
Contacts
Yucheng Su
[email protected]
+886-2-2365-3329

A7328

   First Validated: 8/14/2025
Operating Environment Algorithm Capabilities
AMD Zynq UltraScale+ MPSoC ZCU104 Expand
    		AES-ECB Expand
    AMD Zynq UltraScale+ MPSoC ZCU104 Expand
      		ML-DSA KeyGen Expand
      AMD Zynq UltraScale+ MPSoC ZCU104 Expand
        		ML-DSA SigGen Expand
        AMD Zynq UltraScale+ MPSoC ZCU104 Expand
          		ML-DSA SigVer Expand
          AMD Zynq UltraScale+ MPSoC ZCU104 Expand
            		ML-KEM EncapDecap Expand
            AMD Zynq UltraScale+ MPSoC ZCU104 Expand
              		ML-KEM KeyGen Expand
              AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                		SHA3-224 Expand
                AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                  		SHA3-256 Expand
                  AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                    		SHA3-384 Expand
                    AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                      		SHA3-512 Expand
                      AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                        		SHAKE-128 (FIPS 202) Expand
                        AMD Zynq UltraScale+ MPSoC ZCU104 Expand
                          		SHAKE-256 (FIPS 202) Expand

                          Created October 05, 2016, Updated April 13, 2026