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Cryptographic Algorithm Validation Program CAVP

Description
Microsemi's SHA-2 and HMAC reusable IP core for ASICs and FPGAs is throughput optimized and supports any combination of SHA-2 algorithms, bit-length keys and messages, as well as "online algorithm" operation. This core is developed by cleared US citizens for Government/Defense systems.
Version
4.4 (Firmware)
Type
SOFTWARE
Vendor
Microsemi Corporation
1281 Win Hentschel Blvd
West Lafayette, IN 47906
USA
Contacts
Michael Mehlberg
[email protected]
(571) 319-3343
Fax: (765) 775-1038
General Inquiries
[email protected]
(765) 775-1004
Fax: (765) 775-1038

SHS 2035

   First Validated: 3/29/2013
Operating Environment Algorithm Capabilities
Mentor Graphics Modelsim PE 6.6 Revision: 2010.01 SHA2-224 Expand
Mentor Graphics Modelsim PE 6.6 Revision: 2010.01 SHA2-256 Expand
Mentor Graphics Modelsim PE 6.6 Revision: 2010.01 SHA2-384 Expand
Mentor Graphics Modelsim PE 6.6 Revision: 2010.01 SHA2-512 Expand

Created October 05, 2016, Updated September 22, 2026