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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
7 Series and Zynq AES/MAC
Description
A Verilog implementation that has been synthesized into our 7 Series and Zynq products. This implementation has been governed in our internal revision control system. This implementation can be simulated via a synopsys VCS simulation/testbench framework.
Version
7 Series and Zynq
Type
HARDWARE
Vendor
Advanced Micro Devices (AMD)
2485 Augustine Drive
Santa Clara, CA 95054
USA
Contacts
FIPS Contact
FIPS@amd.com
+1 408-749-4000

SHS 2034

   First Validated: 3/29/2013
Operating Environment Algorithm Capabilities
N/A SHA2-256 Expand

HMAC 1465

   First Validated: 3/29/2013
Operating Environment Algorithm Capabilities
N/A HMAC-SHA2-256 Expand

AES 2363

   First Validated: 3/29/2013
Operating Environment Algorithm Capabilities
N/A AES-CBC Expand

Created October 05, 2016, Updated March 07, 2023