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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Xilinx LogiCORE IP - AES Lite v1.0
Description
The Xilinx AES Lite IP core provides a light-weight implementation of AES with a wide range of configuration options for designs that are constrained on logic resources.
Version
v1.0
Type
FIRMWARE
Vendor
Advanced Micro Devices (AMD)
2485 Augustine Drive
Santa Clara, CA 95054
USA
Contacts
FIPS Contact
[email protected]
+1 408-749-4000

C1609

   First Validated: 3/3/2020
Operating Environment Algorithm Capabilities
QuestaSim 10.7c Expand
    		AES-CFB128 Expand
    QuestaSim 10.7c Expand
      		AES-ECB Expand
      QuestaSim 10.7c Expand
        		AES-XTS Expand
        QuestaSim 10.7c Expand
          		AES-XTS Expand

          Created October 05, 2016, Updated April 03, 2025